284 lines
5.6 KiB
ArmAsm
284 lines
5.6 KiB
ArmAsm
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/*
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dct64_neon_float: ARM NEON optimized dct64 (float output version)
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copyright 1995-2010 by the mpg123 project - free software under the terms of the LGPL 2.1
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see COPYING and AUTHORS files in distribution or http://mpg123.org
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initially written by Taihei Monma
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*/
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#include "mangle.h"
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#ifndef _M_ARM
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.code 32
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#endif
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#ifndef __APPLE__
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.fpu neon
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#endif
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.text
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ALIGN16
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costab_arm:
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.word 1056974725
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.word 1057056395
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.word 1057223771
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.word 1057485416
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.word 1057855544
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.word 1058356026
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.word 1059019886
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.word 1059897405
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.word 1061067246
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.word 1062657950
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.word 1064892987
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.word 1066774581
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.word 1069414683
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.word 1073984175
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.word 1079645762
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.word 1092815430
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.word 1057005197
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.word 1057342072
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.word 1058087743
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.word 1059427869
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.word 1061799040
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.word 1065862217
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.word 1071413542
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.word 1084439708
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.word 1057128951
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.word 1058664893
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.word 1063675095
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.word 1076102863
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.word 1057655764
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.word 1067924853
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.word 1060439283
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.word 1060439283
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ALIGN4
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GLOBAL_SYMBOL ASM_NAME(INT123_dct64_real_neon)
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#ifdef __ELF__
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.type ASM_NAME(INT123_dct64_real_neon), %function
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#endif
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ASM_NAME(INT123_dct64_real_neon):
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vpush {q4-q7}
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adr r3, costab_arm
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vld1.32 {q0, q1}, [r2]!
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vld1.32 {q2, q3}, [r2]!
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vld1.32 {q4, q5}, [r2]!
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vld1.32 {q6, q7}, [r2]
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vld1.32 {q12, q13}, [r3, :128]!
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vld1.32 {q14, q15}, [r3, :128]!
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vrev64.32 q4, q4
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vrev64.32 q5, q5
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vrev64.32 q6, q6
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vrev64.32 q7, q7
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vswp d8, d9
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vswp d10, d11
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vswp d12, d13
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vswp d14, d15
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vsub.f32 q8, q0, q7
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vsub.f32 q9, q1, q6
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vsub.f32 q10, q2, q5
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vsub.f32 q11, q3, q4
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vadd.f32 q0, q0, q7
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vadd.f32 q1, q1, q6
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vadd.f32 q2, q2, q5
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vadd.f32 q3, q3, q4
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vmul.f32 q4, q8, q12
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vmul.f32 q5, q9, q13
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vmul.f32 q6, q10, q14
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vmul.f32 q7, q11, q15
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vld1.32 {q12, q13}, [r3, :128]!
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vld1.32 {q14, q15}, [r3, :128]
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vrev64.32 q2, q2
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vrev64.32 q3, q3
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vrev64.32 q6, q6
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vrev64.32 q7, q7
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vswp d4, d5
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vswp d6, d7
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vswp d12, d13
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vswp d14, d15
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vsub.f32 q8, q0, q3
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vsub.f32 q9, q1, q2
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vsub.f32 q10, q4, q7
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vsub.f32 q11, q5, q6
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vadd.f32 q0, q0, q3
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vadd.f32 q1, q1, q2
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vadd.f32 q4, q4, q7
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vadd.f32 q5, q5, q6
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vmul.f32 q2, q8, q12
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vmul.f32 q3, q9, q13
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vmul.f32 q6, q10, q12
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vmul.f32 q7, q11, q13
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vrev64.32 q1, q1
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vrev64.32 q3, q3
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vrev64.32 q5, q5
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vrev64.32 q7, q7
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vswp d2, d3
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vswp d6, d7
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vswp d10, d11
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vswp d14, d15
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vsub.f32 q8, q0, q1
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vsub.f32 q9, q2, q3
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vsub.f32 q10, q4, q5
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vsub.f32 q11, q6, q7
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vadd.f32 q0, q0, q1
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vadd.f32 q2, q2, q3
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vadd.f32 q4, q4, q5
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vadd.f32 q6, q6, q7
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vmul.f32 q1, q8, q14
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vmul.f32 q3, q9, q14
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vmul.f32 q5, q10, q14
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vmul.f32 q7, q11, q14
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vdup.32 q12, d31[0]
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vmov d31, d30
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vswp d1, d2
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vswp d5, d6
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vswp d9, d10
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vswp d13, d14
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vrev64.32 q1, q1
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vrev64.32 q3, q3
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vrev64.32 q5, q5
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vrev64.32 q7, q7
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vsub.f32 q8, q0, q1
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vsub.f32 q9, q2, q3
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vsub.f32 q10, q4, q5
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vsub.f32 q11, q6, q7
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vadd.f32 q0, q0, q1
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vadd.f32 q2, q2, q3
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vadd.f32 q4, q4, q5
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vadd.f32 q6, q6, q7
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vmul.f32 q1, q8, q15
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vmul.f32 q3, q9, q15
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vmul.f32 q5, q10, q15
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vmul.f32 q7, q11, q15
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vtrn.32 q0, q1
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vtrn.32 q2, q3
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vtrn.32 q4, q5
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vtrn.32 q6, q7
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vsub.f32 q8, q0, q1
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vsub.f32 q9, q2, q3
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vsub.f32 q10, q4, q5
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vsub.f32 q11, q6, q7
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vadd.f32 q0, q0, q1
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vadd.f32 q2, q2, q3
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vadd.f32 q4, q4, q5
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vadd.f32 q6, q6, q7
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vmul.f32 q1, q8, q12
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vmul.f32 q3, q9, q12
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vmul.f32 q5, q10, q12
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vmul.f32 q7, q11, q12
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vtrn.32 q0, q1
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vtrn.32 q2, q3
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vtrn.32 q4, q5
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vtrn.32 q6, q7
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vswp d1, d2
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vswp d5, d6
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vswp d9, d10
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vswp d13, d14
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vshr.u64 d16, d1, #32
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vshr.u64 d17, d3, #32
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vshr.u64 d18, d5, #32
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vshr.u64 d19, d7, #32
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vadd.f32 d1, d1, d16
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vadd.f32 d3, d3, d17
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vadd.f32 d5, d5, d18
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vadd.f32 d7, d7, d19
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vshr.u64 d20, d9, #32
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vshr.u64 d21, d11, #32
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vshr.u64 d22, d13, #32
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vshr.u64 d23, d15, #32
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vadd.f32 d9, d9, d20
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vadd.f32 d11, d11, d21
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vadd.f32 d13, d13, d22
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vadd.f32 d15, d15, d23
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vshr.u64 d16, d2, #32
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vshr.u64 d18, d6, #32
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vshr.u64 d20, d10, #32
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vshr.u64 d22, d14, #32
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vext.8 q8, q1, q8, #8
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vext.8 q9, q3, q9, #8
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vext.8 q10, q5, q10, #8
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vext.8 q11, q7, q11, #8
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vadd.f32 q1, q1, q8
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vadd.f32 q3, q3, q9
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vadd.f32 q5, q5, q10
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vadd.f32 q7, q7, q11
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vshr.u64 d16, d4, #32
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vshr.u64 d18, d12, #32
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vext.8 q8, q2, q8, #8
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vext.8 q9, q6, q9, #8
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vadd.f32 q2, q2, q3
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vadd.f32 q6, q6, q7
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vadd.f32 q3, q3, q8
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vadd.f32 q7, q7, q9
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vrev64.32 q8, q4
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vshr.u64 d19, d9, #32
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vext.8 d17, d17, d16, #4
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vswp d9, d10
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vswp d13, d14
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vtrn.32 q4, q5
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vtrn.32 q6, q7
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vmov d16, d9
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vmov d18, d11
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vadd.f32 q4, q6
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vadd.f32 q5, q7
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vadd.f32 q6, q8
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vadd.f32 q7, q9
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mov r3, #64
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vst1.32 {d0[1]}, [r0, :32], r3
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vst1.32 {d13[1]}, [r0, :32], r3
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vst1.32 {d7[0]}, [r0, :32], r3
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vst1.32 {d9[1]}, [r0, :32], r3
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vst1.32 {d3[0]}, [r0, :32], r3
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vst1.32 {d12[1]}, [r0, :32], r3
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vst1.32 {d5[0]}, [r0, :32], r3
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vst1.32 {d8[1]}, [r0, :32], r3
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vst1.32 {d1[0]}, [r0, :32], r3
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vst1.32 {d13[0]}, [r0, :32], r3
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vst1.32 {d6[0]}, [r0, :32], r3
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vst1.32 {d9[0]}, [r0, :32], r3
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vst1.32 {d2[0]}, [r0, :32], r3
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vst1.32 {d12[0]}, [r0, :32], r3
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vst1.32 {d4[0]}, [r0, :32], r3
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vst1.32 {d8[0]}, [r0, :32], r3
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vst1.32 {d0[0]}, [r0, :32]
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vst1.32 {d0[1]}, [r1, :32], r3
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vst1.32 {d10[0]}, [r1, :32], r3
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vst1.32 {d4[1]}, [r1, :32], r3
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vst1.32 {d14[0]}, [r1, :32], r3
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vst1.32 {d2[1]}, [r1, :32], r3
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vst1.32 {d11[0]}, [r1, :32], r3
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vst1.32 {d6[1]}, [r1, :32], r3
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vst1.32 {d15[0]}, [r1, :32], r3
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vst1.32 {d1[1]}, [r1, :32], r3
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vst1.32 {d10[1]}, [r1, :32], r3
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vst1.32 {d5[1]}, [r1, :32], r3
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vst1.32 {d14[1]}, [r1, :32], r3
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vst1.32 {d3[1]}, [r1, :32], r3
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vst1.32 {d11[1]}, [r1, :32], r3
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vst1.32 {d7[1]}, [r1, :32], r3
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vst1.32 {d15[1]}, [r1, :32]
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vpop {q4-q7}
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bx lr
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NONEXEC_STACK
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