184 lines
4 KiB
ArmAsm
184 lines
4 KiB
ArmAsm
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/*
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synth_neon_accurate: ARM NEON optimized synth (MPEG compliant 16-bit output version)
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copyright 1995-2010 by the mpg123 project - free software under the terms of the LGPL 2.1
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see COPYING and AUTHORS files in distribution or http://mpg123.org
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initially written by Taihei Monma
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*/
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#include "mangle.h"
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#define WINDOW r0
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#define B0 r1
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#define SAMPLES r2
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/*
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int synth_1to1_real_neon_accurate_asm(real *window, real *b0, real *samples, int bo1);
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return value: number of clipped samples (0)
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*/
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.code 32
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#ifndef __APPLE__
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.fpu neon
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#endif
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.text
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.globl ASM_NAME(INT123_synth_1to1_neon_accurate_asm)
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#ifdef __ELF__
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.type ASM_NAME(INT123_synth_1to1_neon_accurate_asm), %function
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#endif
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ASM_NAME(INT123_synth_1to1_neon_accurate_asm):
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push {r4-r6, lr}
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vpush {q4-q7}
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mov r6, sp
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sub sp, sp, #16
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bic sp, #0xff
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add WINDOW, WINDOW, #64
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sub WINDOW, WINDOW, r3, lsl #2
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mov r3, #4
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mov r4, #128
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mov r5, #64
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1:
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vld1.32 {q0,q1}, [WINDOW], r4
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vld1.32 {q2,q3}, [WINDOW], r4
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vld1.32 {q4,q5}, [WINDOW], r4
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vld1.32 {q6,q7}, [WINDOW]
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sub WINDOW, WINDOW, #352
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vld1.32 {q8,q9}, [B0, :128], r5
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vld1.32 {q10,q11}, [B0, :128], r5
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vld1.32 {q12,q13}, [B0, :128], r5
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vld1.32 {q14,q15}, [B0, :128]
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vswp q1, q4
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vswp q3, q6
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sub B0, B0, #160
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vmul.f32 q0, q0, q8
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vmul.f32 q2, q2, q10
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vmul.f32 q1, q1, q12
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vmul.f32 q3, q3, q14
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vmla.f32 q0, q4, q9
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vmla.f32 q2, q6, q11
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vmla.f32 q1, q5, q13
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vmla.f32 q3, q7, q15
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vld1.32 {q4,q5}, [WINDOW], r4
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vld1.32 {q6,q7}, [WINDOW], r4
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vld1.32 {q8,q9}, [WINDOW], r4
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vld1.32 {q10,q11}, [B0, :128], r5
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vld1.32 {q12,q13}, [B0, :128], r5
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vld1.32 {q14,q15}, [B0, :128], r5
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vswp q5, q6
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vswp q11, q12
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vmla.f32 q0, q4, q10
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vmla.f32 q2, q5, q11
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vmla.f32 q1, q8, q14
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vld1.32 {q4,q5}, [WINDOW]
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vld1.32 {q10,q11}, [B0, :128]!
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add WINDOW, WINDOW, #96
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vmla.f32 q3, q4, q10
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vmla.f32 q0, q6, q12
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vmla.f32 q2, q7, q13
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vmla.f32 q1, q9, q15
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vmla.f32 q3, q5, q11
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vmov.i32 q4, #0x4b000000
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vmvn.i32 q5, #0xb9000000
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vorr.i32 q4, #0x00400000
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vpadd.f32 d0, d0, d1
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vpadd.f32 d4, d4, d5
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vpadd.f32 d2, d2, d3
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vpadd.f32 d6, d6, d7
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vld1.32 {q6}, [sp, :128]
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vpadd.f32 d0, d0, d4
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vpadd.f32 d1, d2, d6
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vadd.f32 q3, q0, q4
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vacgt.f32 q5, q0, q5
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vld2.16 {d4,d5}, [SAMPLES]
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vshl.i32 q3, q3, #10
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vqshrn.s32 d3, q3, #10
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vshr.u32 q5, q5, #31
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vst2.16 {d3,d5}, [SAMPLES]!
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vadd.i32 q5, q5, q6
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vst1.32 {q5}, [sp, :128]
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subs r3, r3, #1
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bne 1b
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mov r3, #4
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mov r5, #-64
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1:
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vld1.32 {q0,q1}, [WINDOW], r4
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vld1.32 {q2,q3}, [WINDOW], r4
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vld1.32 {q4,q5}, [WINDOW], r4
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vld1.32 {q6,q7}, [WINDOW]
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sub WINDOW, WINDOW, #352
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vld1.32 {q8,q9}, [B0, :128], r5
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vld1.32 {q10,q11}, [B0, :128], r5
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vld1.32 {q12,q13}, [B0, :128], r5
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vld1.32 {q14,q15}, [B0, :128]
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vswp q1, q4
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vswp q3, q6
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add B0, B0, #224
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vmul.f32 q0, q0, q8
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vmul.f32 q2, q2, q10
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vmul.f32 q1, q1, q12
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vmul.f32 q3, q3, q14
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vmla.f32 q0, q4, q9
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vmla.f32 q2, q6, q11
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vmla.f32 q1, q5, q13
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vmla.f32 q3, q7, q15
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vld1.32 {q4,q5}, [WINDOW], r4
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vld1.32 {q6,q7}, [WINDOW], r4
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vld1.32 {q8,q9}, [WINDOW], r4
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vld1.32 {q10,q11}, [B0, :128], r5
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vld1.32 {q12,q13}, [B0, :128], r5
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vld1.32 {q14,q15}, [B0, :128], r5
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vswp q5, q6
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vswp q11, q12
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vmla.f32 q0, q4, q10
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vmla.f32 q2, q5, q11
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vmla.f32 q1, q8, q14
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vld1.32 {q4,q5}, [WINDOW]
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vld1.32 {q10,q11}, [B0, :128]
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add WINDOW, WINDOW, #96
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sub B0, B0, #96
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vmla.f32 q3, q4, q10
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vmla.f32 q0, q6, q12
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vmla.f32 q2, q7, q13
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vmla.f32 q1, q9, q15
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vmla.f32 q3, q5, q11
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vmov.i32 q4, #0x4b000000
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vmvn.i32 q5, #0xb9000000
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vorr.i32 q4, #0x00400000
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vpadd.f32 d0, d0, d1
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vpadd.f32 d4, d4, d5
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vpadd.f32 d2, d2, d3
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vpadd.f32 d6, d6, d7
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vld1.32 {q6}, [sp, :128]
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vpadd.f32 d0, d0, d4
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vpadd.f32 d1, d2, d6
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vadd.f32 q3, q0, q4
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vacgt.f32 q5, q0, q5
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vld2.16 {d4,d5}, [SAMPLES]
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vshl.i32 q3, q3, #10
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vqshrn.s32 d3, q3, #10
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vshr.u32 q5, q5, #31
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vst2.16 {d3,d5}, [SAMPLES]!
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vadd.i32 q5, q5, q6
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vst1.32 {q5}, [sp, :128]
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subs r3, r3, #1
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bne 1b
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vld1.32 {q0}, [sp, :128]
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vpadd.i32 d0, d0, d1
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vpadd.i32 d0, d0, d0
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vmov.32 r0, d0[0]
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mov sp, r6
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vpop {q4-q7}
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pop {r4-r6, pc}
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NONEXEC_STACK
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